/*Yipeng Huang and Scott Rogowski*/
/*yh2315 smr2167*/

//Translates the opcode into the control lines
module Control(opcode,register_destination,ALU_source,mem_to_register,register_write,memory_read,memory_write,branch,jump,ALU_op,bunch_debug);

	input [5:0] opcode;		
	reg [9:0] bunch;
	
	
	//Assign logic to the bunch case by case
	always @(*) begin
		case (opcode)
			6'b000000: bunch = 10'b1011000010; //add
			6'b100011: bunch = 10'b0101100000; //lw
			6'b101011: bunch = 10'b0110010000; //sw
			6'b000100: bunch = 10'b0010001001; //beq
			6'b001000: bunch = 10'b0111000010; //addi  I figured out this one all on my own so it should be checked...
			6'b000010: bunch = 10'b0000000100; //jmp
			default:   bunch = 10'b0000000000; //noop If we get something that we don't recognize, this is a stall.  Make sure that nothing is being written to
			endcase
		end
	
	//Divide up and output the bunch
	output register_destination;assign register_destination = bunch[9]; //0 instructions[20:16] | 1 instructions[15:11] : write_register
	output ALU_source;			assign ALU_source 			= bunch[8]; //0 read_data_1 | 1 instructions : ALU_src_1
	output mem_to_register;		assign mem_to_register 		= bunch[7]; //0 read_memory | 1 ALU_result : register_write_data
	output register_write;		assign register_write 		= bunch[6]; //0 The register is NOT writable | 1 The register is writable
	output memory_read;			assign memory_read 			= bunch[5]; //0 Memory NOT readable | 1 Memory is readable
	output memory_write;		assign memory_write 		= bunch[4]; //0 Memory NOT writable | 1 Memory is writable
	output branch;				assign branch 				= bunch[3]; //0 DO NOT BRANCH | 1 A branch is taken if this is true and the two ALU values are equal : jump MUX
	output jump;				assign jump 				= bunch[2]; //0 PC+4 or branch target depending on previous branch control | jump target : Instruction memory
	output [1:0] ALU_op;		assign ALU_op[1] 			= bunch[1]; //10 is Add, 01 is subtract, 00 is add [TODO is this right?] 
								assign ALU_op[0]			= bunch[0];
	output [9:0] bunch_debug;	assign bunch_debug = bunch;

	endmodule
